The present technique relates to an apparatus and method for maintaining address translation data within an address translation cache.
It is known to provide data processing systems which incorporate an address translation cache, such as a translation lookaside buffer (TLB), to store address translation data relating to the translation of, for example, virtual addresses to physical addresses. The address translation data can also provide attribute data regarding the memory accesses being made, such as permission data and memory attributes. Whilst the provision of an address translation cache is useful in improving performance by reducing the number of slow page table walks required, the address translation cache itself consumes circuit resources.
It is known to create coalesced TLB entries in the specific situation where multiple descriptors meet page alignment criteria and have the same attribute data. However, whilst creating coalesced entries can allow more efficient use of the address translation cache resources to be made, it is often the case that the existing requirements for coalescing are not present, and hence the opportunities to create coalesced entries are limited.
Accordingly, it is desirable to make more efficient use of the capacity of the address translation cache.